Complementary metal oxide semiconductor (CMOS) transistors are the building blocks for integrated circuits (ICs). CMOS devices continue to be scaled to smaller sizes with the goals of increasing both device speed and IC density. Exemplary CMOS devices include N-type metal oxide semiconductor (NMOS) and P-type metal oxide semiconductor (PMOS) transistors. A CMOS transistor generally comprises a semiconductor substrate, a channel layer above the semiconductor substrate, a gate oxide layer and a gate stack above the channel layer, and source and drain diffusion regions in the surface of the semiconductor substrate.
A good understanding of the matching behavior of components available in a particular IC technology is critical in designing ICs. With the advancements in technology leading to smaller feature sizes and more stringent design constraints, device mismatch considerations are becoming increasingly important. Thus, as semiconductor feature size decreases, statistical variations in circuitry characteristics, caused by statistical variations in semiconductor processes can become increasingly severe. An accurate model of current mismatch is an integral part of any computer aided design (CAD) environment as it enables a designer to make high-level design trade-offs, such as area of transistor versus current mismatch, etc., at an early stage of a design cycle. Such models also allow the designer to accurately predict circuit yield and/or improve that yield.
Current mismatch in a certain component can generally be defined as a variation in the value of identically designed components. Some of the causes of current mismatch are edge effects, implantation and surface state charges, oxide effects, mobility effects, poly density gradient effects, etc. Even though the importance of current matching is widely recognized in the industry there remains a need to provide a tool or model based on silicon to predict the impact of poly density gradient effects on MOS arrays